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HT48CA0 8-bit microcontroller pin assignment features operating voltage: 2.2v~3.6v ten bidirectional i/o lines six schmitt trigger input lines one carrier output (1/2 or 1/3 duty) on-chip crystal and rc oscillator watchdog timer 1k 14 program rom 32 8 data ram low voltage reset function halt function and wake-up feature reduce power consumption 62 powerful instructions up to 1 m s instruction cycle with 4mhz system clock all instructions in 1 or 2 machine cycles 14-bit table read instructions one-level subroutine nesting bit manipulation instructions general description the HT48CA0 is an 8-bit high performance risc-like microcontroller specifically designed for multiple i/o product applications. the de- vice is particularly suitable for use in products such as remote controllers, fan/light control- lers, washing machine controllers, scales, toys and various subsystem controllers. a halt fea- ture is included to reduce power consumption. 1 23rd july 98
block diagram HT48CA0 2 23rd july 98
pad description pad no. pad name i/o mask option function 1, 22 pb0, pb1 i/o wake-up or none 2-bit bidirectional input/output lines with pull-high resistors. each bit can be determined as nmos output or schmitt trigger input by software instructions. each bit can also be configured as wake-up input by mask option. 2 pc0/rem o level or carrier level or carrier output pin pc0 can be set as cmos output pin or carrier output pin by mask option. 3 vdd positive power supply 6 vss negative power supply, gnd 7 res i schmitt trigger reset input. active low. 13~8 pb2~pb7 i wake-up or none 6-bit schmitt trigger input lines with pull-high resistors. each bit can be configured as a wake-up input by mask option. 21~14 pa0~pa7 i/o bidirectional 8-bit input/output port with pull-high resistors. each bit can be determined as nmos output or schmitt trigger input by software instructions. osc1 osc2 i o crystal or rc osc1, osc2 are connected to an rc network or a crystal (determined by mask option) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock (nmos open drain output). HT48CA0 3 23rd july 98
pad assignment * the ic substrate should be connected to vss in the pcb layout artwork. * the tmr pad must be bonded to vdd or vss if the tmr pad is not used. absolute maximum ratings* supply voltage ................................. C0.3v to 4v storage temperature................. C50 c to 125 c input voltage................. v ss C0.3v to v dd +0.3v operating temperature............... C25 c to 70 c *note: these are stress ratings only. stresses exceeding the range specified under absolute maxi- mum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT48CA0 4 23rd july 98
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.2 3.6 v i dd operating current 3v no load, f sys =4mhz 0.7 1.5 ma i stb standby current 3v no load, system halt 1 m a v il1 input low voltage for i/o ports 3v 0 1.05 v v ih1 input high voltage for i/o ports 3v 1.95 3 v v il2 input low voltage ( res) 3v 1.5 v v ih2 input high voltage ( res) 3v 2.4 v i ol i/o ports sink current 3v v ol =0.3v 1.5 2.5 ma i oh i/o ports source current 3v v oh =2.7v C1 C1.5 ma r ph1 pull-high resistance of pa port, pb0~pb1 and res 3v 60 k w r ph2 pull-high resistance of pb2~pb7 3v 60 k w v lv r low voltage reset 3v 1.8 2.0 2.2 v a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 3v 400 4000 khz t res external reset low pulse width 1 m s t sst system start-up timer period power-up or wake-up from halt 1024t sys note: t sys =1/f sys HT48CA0 5 23rd july 98
application circuit notes: it is recommended that a 0.1 m f decoupling capacitor is placed between vss and vdd. if the crystal has a value above 1mhz the capacitors are not required. HT48CA0 6 23rd july 98
system architecture execution flow the HT48CA0 system clock can be derived from a crystal/ceramic resonator oscillator. it is in- ternally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipe- lined in such a way that a fetch takes one in- struction cycle while decoding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruction to effectively execute within one cycle. if an in- struction changes the program counter, two cy- cles are required to complete the instruction. program counter C pc the 10-bit program counter (pc) controls the sequence in which the instructions stored in program rom are executed and its contents specify a maximum of 1024 addresses. after accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip execution, loading pcl register, subrou- tine call, initial reset or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each in- struction. the conditional skip is activated by instruction. once the condition is met, the next instruction, fetched during the current instruction execu- tion, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise pro- ceed with the next instruction. the lower byte of the program counter (pcl) is a readable and writeable register (06h). mov- ing data into the pcl performs a short jump. the destination will be within 256 locations. when a control transfer takes place, an addi- tional dummy cycle is required. program memory C rom the program memory is used to store the pro- gram instructions which are to be executed. it also contains data and table and is organized into 1024 14 bits, addressed by the program counter and table pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for the initialization program. after chip reset, the program always begins execution at location 000h. table location any location in the rom space can be used as look-up tables. the instructions tabrdc [m] (the current page, 1 page=256 words) and tabrdl [m] (the last page) transfer the con- tents of the lower-order byte to the specified execution flow HT48CA0 7 23rd july 98
mode program counter *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 000000000 0 skip pc+2 loading pcl *9 *8 @7@6@5@4@3@2@1 @0 jump, call branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter notes: *9~*0: program counter bits #9~#0: instruction code bits s9~s0: stack register bits @7~@0: pcl bits data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of tblh, the remaining 2 bits are read as 0. the table higher-order byte register (tblh) is read only. the table pointer (tblp) is a read/write register (07h), where p indicates the table location. before accessing the table, the location must be placed in tblp. the tblh is read only and cannot be restored. all table related instruc- tions need 2 cycles to complete the operation. these areas may function as normal program memory depending upon the requirements. stack register C stack this is a special part of the memory used to save the contents of the program counter (pc) only. the stack is organized into one level and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor write- able. at a subroutine call the contents of the program counter are pushed onto the stack. at the end of a subroutine signaled by a return instruction (ret), the program counter is re- stored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a call is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent return address is stored). data memory C ram the data memory is designed with 42 8 bits. the data memory is divided into two functional groups: special function registers and general purpose data memory (32 8). most of them are read/write, but some are read only. program memory HT48CA0 8 23rd july 98
instruction(s) table location *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location notes: *9~*0: table location bits @7~@0: table pointer bits p9~p8: current program counter bits the special function registers include the indirect addressing register (00h), the memory pointer register (mp;01h), the accumulator (acc;05h) the program counter lower-order byte register (pcl;06h), the table pointer (tblp;07h), the ta- ble higher-order byte register (tblh;08h), the status register (status;0ah) and the i/o regis- ters (pa;12h, pb;14h, pc;16h). the remaining space before the 20h is reserved for future ex- panded usage and reading these locations will return the result 00h. the general purpose data memory, addressed from 20h to 3fh, is used for data and control information under instruction command. all data memory areas can handle arithmetic, logic, increment, decrement and rotate opera- tions directly. except for some dedicated bits, each bit in the data memory can be set and reset by the set [m].i and clr [m].i instructions, respectively. they are also indirectly accessible through memory pointer register (mp;01h). indirect addressing register location 00h is an indirect addressing register that is not physically implemented. any read/write operation of [00h] accesses data memory pointed to by mp (01h). reading loca- tion 00h itself indirectly will return the result 00h. writing indirectly results in no operation. the memory pointer register mp (01h) is a 6-bit register. the bit 7~6 of mp is undefined and reading will return the result 1. any writing operation to mp will only transfer the lower 6-bit data to mp. ram mapping HT48CA0 9 23rd july 98
accumulator the accumulator closely relates to alu opera- tions. it is also mapped to location 05h of the data memory and is capable of carrying out immediate data operations. data movement be- tween two data memory locations has to pass through the accumulator. arithmetic and logic unit C alu this circuit performs 8-bit arithmetic and logic operation. the alu provides the following func- tions. arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the contents of the status register. status register C status this 8-bit status register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pd) and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pd flags, bits in the status register can be altered by instruc- tions like most other register. any data written into the status register will not change the to or pd flags. in addition it should be noted that operations related to the status register may give different results from those intended. the to and pd flags can only be changed by the watchdog timer overflow, chip power-up, clear- ing the watchdog timer and executing the halt instruction. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on executing the subroutine call, the status register will not be automatically pushed onto the stack. if the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. labels bits function c0 c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac 1 ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z2 z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. ov 3 ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pd 4 pd is cleared when either a system power-up or executing the clr wdt instruction. pd is set by executing the halt instruction. to 5 to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6 undefined, read as 0 7 undefined, read as 0 status register HT48CA0 10 23rd july 98
oscillator configuration there are two oscillator circuits in the HT48CA0. both are designed for system clocks; the rc oscillator and the crystal oscillator, which are determined by mask options. no matter what oscillator type is selected, the signal provides the system clock. the halt mode stops the system oscillator and ignores the external sig- nal to conserve power. if an rc oscillator is used, an external resistor between osc1 and vss in needed and the re- sistance must range from 51k w to 1m w . the system clock, divided by 4, is available on osc2, which can be used to synchronize exter- nal logic. the rc oscillator provides the most cost effective solution. however, the frequency of the oscillation may vary with vdd, tempera- ture and the chip itself due to process vari- ations. it is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feed- back and phase shift for the oscillator. no other external components are needed. instead of a crystal, the resonator can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 are required. watchdog timer C wdt the clock source of the wdt is implemented by instruction clock (system clock divided by 4). the clock source is processed by a frequency divider and a prescaller to yield various time out periods. wdt time out period = clock source 2 n where n= 8~11 selected by mask option. this timer is designed to prevent a software malfunction or sequence jumping to an un- known location with unpredictable results. the watchdog timer can be disabled by mask op- tion. if the watchdog timer is disabled, all the executions related to the wdt result in no op- system oscillator watchdog timer HT48CA0 11 23rd july 98
eration and the wdt will lose its protection purpose. in this situation the logic can only be restarted by an external logic. a wdt overflow under normal operation will in- itialize chip reset and set the status bit "to". to clear the contents of the wdt prescaler, three methods are adopted; external reset (a low level to res), software instructions, or a halt instruc- tion. there are two types of software instructions. one type is the single instruction "clr wdt", the other type comprises two instructions, "clr wdt1" and "clr wdt2". of these two types of instructions, only one can be active depending on the mask option clr wdt times selection option. if the clr wdt is selected (i.e.. clrwdt times equal one), any execution of the clr wdt instruction will clear the wdt. in case clr wdt1 and clr wdt2 are chosen (i.e.. clrwdt times equal two), these two instruc- tions must be executed to clear the wdt; other- wise, the wdt may reset the chip due to a time-out. power down operation C halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator turns off and the wdt stops. the contents of the on-chip ram and regis- ters remain unchanged. wdt prescaler are cleared. all i/o ports maintain their original status. the pd flag is set and the to flag is cleared. the system can quit the halt mode by means of an external reset or an external falling edge signal on port b. an external reset causes a device initialization. examining the to and pd flags, the reason for chip reset can be deter- mined. the pd flag is cleared when the system powers up or execute the clr wdt instruction and is set when the halt instruction is exe- cuted. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the pc (program counter) and sp, the others keep their original status. the port b wake-up can be considered as a continuation of normal execution. each bit in port b can be independently selected to wake up the device by the mask option. awakening from an i/o port stimulus, the program will resume execution of the next instruction. once a wake-up event(s) occurs, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy cycle pe- riod will be inserted after the wake-up. to minimize power consumption, all i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation some registers remain unchanged during reset conditions. most registers are reset to the in- itial condition when the reset conditions are met. by examining the pd and to flags, the program can distinguish between different chip resets. to pd reset conditions 00 res reset during power-up uu res reset during normal operation 01 res wake-up halt 1u wdt time-out during normal operation note: u means unchanged. HT48CA0 12 23rd july 98
to guarantee that the system oscillator has started and stabilized, the sst (system start- up timer) provides an extra-delay of 1024 sys- tem clock pulses when the system powers up or when the system awakes from a halt state. when a system power up occurs, an sst delay is added during the reset period. but when the reset comes from the res pin, the sst delay is disabled. any wake-up from halt will enable the sst delay. the functional unit chip reset status is shown below. pc 000h wdt prescaler clear input/output ports input mode sp points to the top of the stack carrier output low level reset configuration reset circuit the chip reset status of the registers is summarized in the following table: register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) pc (program counter) 000h 000h 000h 000h mp -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 pc ---- ---1 ---- ---1 ---- ---1 ---- ---1 notes: u means unchanged x means unknown reset timing chart HT48CA0 13 23rd july 98
low voltage reset lvr the HT48CA0 provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~2.2v, such as changing a battery, the lvr will automatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~2.2v) has to remain in their original state to exceed 1 ms. if the low voltage state does not exceed 1 ms, the lvr will ignore it and do not perform a reset func- tion. the lvr uses the or function with the exter- nal res signal to perform chip reset. during halt mode, if the lvr occurs, the device will wake-up and the pd flag will be set as 1, the same as the external res. because the operating voltage (v dd ) is 2.2v~3.6v and the lvr operating voltage (v lv r ) is 0.9v~2.2v, therefore one margin volt- age about 0.1v is needed for proper chip opera- tion. the relationship between v dd and v lv r is shown below. note: v opr is the voltage range for proper chip operation at 4mhz system clock. carrier the HT48CA0 provides a carrier output which shares the pin with pc0. it can be selected to be a carrier output (rem) or level output pin (pc0) by mask option. if the carrier output option is selected, setting pc0=0 to enable carrier out- put and setting pc0=1 to disable it at low level output. low voltage reset *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since the low voltage has to maintain in its original state and exceed 1 ms, therefore 1 ms delay is needed to enter the reset mode. HT48CA0 14 23rd july 98
carrier/level output pb input lines the clock source of the carrier is implemented by instruction clock (system clock divided by 4) and processed by a frequency divider to yield various carry frequency. carry frequency= clock source m 2 n where m=2 or 3 and n=0~3, both are selected by mask option. if m=2, the duty cycle of the car- rier output is 1/2 duty. if m=3, the duty cycle of the carrier output can be 1/2 duty or 1/3 duty also determined by mask option (with the ex- ception of n=0). detailed selection of the carrier duty is shown below: m 2 n duty cycle 2, 4, 8, 16 1/2 3 1/3 6, 12, 24 1/2 or 1/3 input/output ports there are an 8-bit bidirectional input/output port, a 6-bit input with 2-bit i/o port and one-bit output port in the HT48CA0, labeled pa, pb and pc which are mapped to [12h], [14h], [16h] of the ram, respectively. each bit of pa can be selected as nmos output or schmitt trigger with pull-high resistor by software instruction. pb0~pb1 have the same structure with pa, while pb2~pb7 can only be used for input op- eration (schmitt trigger with pull-high resis- tors). pc is only one-bit output port shares the pin with carrier output. if the level option is selected, the pc is cmos output. both pa and pb for the input operation, these ports are non-latched, that is, the inputs should be ready at the t2 rising edge of the instruction mov a, [m] (m=12h or 14h). for pa, pb0~pb1 and pc output operation, all data are latched and remain unchanged until the output latch is rewritten. when the pa and pb0~pb1 is used for input operation, it should be noted that before read- ing data from pads, a 1 should be written to the related bits to disable the nmos device. that is, the instruction set [m].i (i=0~7 for pa, i=0~1 for pb) is executed first to disable related nmos device, and then mov a, [m] to get stable data. HT48CA0 15 23rd july 98
pa, pb input/output lines after chip reset, pa and pb remain at a high level input line while pc remain at high level output, if the level option is selected. each bit of pa, pb0~pb1 and pc output latches can be set or cleared by the set [m].i and clr [m].i (m=12h, 14h or 16h) instructions respectively. some instructions first input data and then follow the output operations. for example, set [m].i, clr [m], cpl [m], cpla [m] read the entire port states into the cpu, exe- cute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. each line of pb has a wake-up capability to the device by mask option. the highest seven bits of pc are not physically implemented, on reading them a 0 is returned and writing results in a no-operation. HT48CA0 16 23rd july 98
mask option the following table shows eight kinds of mask option in the HT48CA0. all the mask options must be defined to ensure proper system functioning. no. mask option 1 wdt time-out period selection time-out period= clock source 2 n where n=8~11. 2 wdt enable/disable selection. this option is to decide whether the wdt timer is enabled or disabled. 3 clrwdt times selection. this option defines how to clear the wdt by instruction. one time means that the clr wdt instruction can clear the wdt. two times means only if both of the clr wdt1 and clr wdt2 instructions have been executed, the wdt can be cleared. 4 wake-up selection. this option defines the wake-up activity function. external input pins (pb only) all have the capability to wake-up the chip from a halt. 5 carrier/level output selection. this option defines the activity of pc0 to be carrier output or level output. 6 carry frequency selection. carry frequency= clock source ( 2 or 3 ) 2 n where n=0~3. 7 carrier duty selection. there are two types of selection: 1/2 duty or 1/3 duty. if carrier frequency= clock source / (2, 4, 8 or 16), the duty cycle will be 1/2 duty. if carrier frequency= clock source / 3, the duty cycle will be 1/3 duty. if carrier frequency= clock source / (6, 12 or 24), the duty cycle can be 1/2 duty or 1/3 duty. 8 osc type selection. this option is to decide if an rc or crystal oscillator is chosen as system clock. if the crystal oscillator is selected, the xst (crystal start-up timer) default is activated, otherwise the xst is disabled. HT48CA0 17 23rd july 98
instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to register with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry with result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z HT48CA0 18 23rd july 98
mnemonic description instruction cycle flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 none none none none none none none none none none none none HT48CA0 19 23rd july 98
mnemonic description instruction cycle flag affected table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pd to (4) ,pd (4) to (4) ,pd (4) none none to,pd notes: x: 8 bits immediate data m: 7 bits data memory address a: accumulator i: 0~7 number of bits addr: 11 bits program memory address ? : flag(s) is affected - : flag(s) is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (4 system clocks). (2) : if a skip to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (4 system clocks). otherwise the original instruction cycle(s) is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to is set and the pd is cleared. otherwise the to and pd flags remain unchanged. HT48CA0 20 23rd july 98
instruction definition adc a,[m] add data memory and carry to accumulator description the contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. operation acc ? acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? adcm a,[m] add accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. operation [m] ? acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? add a,[m] add data memory to accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc ? acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? add a,x add immediate data to accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc ? acc+x affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? HT48CA0 21 23rd july 98
addm a,[m] add accumulator to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] ? acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory performs a bitwise logical_and operation. the result is stored in the accumulator. operation acc ? acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC and a,x logical and immediate data to accumulator description data in the accumulator and the specified data performs a bitwise logi- cal_and operation. the result is stored in the accumulator. operation acc ? acc and x affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC andm a,[m] logical and data memory with accumulator description data in the specified data memory and the accumulator performs a bitwise logical_and operation. the result is stored in the data memory. operation [m] ? acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC HT48CA0 22 23rd july 98
call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this ad- dress. operation stack ? pc+1 pc ? addr affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC clr [m] clear data memory description the contents of the specified data memory are cleared to zero. operation [m] ? 00h affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to zero. operation [m].i ? 0 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC clr wdt clear watchdog timer description the wdt and the wdt prescaler are cleared (re-counting from zero). the power down bit (pd) and time-out bit (to) are cleared. operation wdt and wdt prescaler ? 00h pd and to ? 0 affected flag(s) tc2 tc1 to pd ov z ac c C C 00CCCC HT48CA0 23 23rd july 98
clr wdt1 preclear watchdog timer description the pd, to flags, wdt and the wdt prescaler are cleared (re-counting from zero), if the other preclear wdt instruction had been executed. only execu- tion of this instruction without the other preclear instruction sets the indi- cating flag which implies this instruction was executed. the pd and to flags remain unchanged. operation wdt and wdt prescaler ? 00h* pd and to ? 0* affected flag(s) tc2 tc1 to pd ov z ac c C C0*0*CCCC clr wdt2 preclear watchdog timer description the pd, to flags, wdt and the wdt prescaler are cleared (re-counting from zero), if the other preclear wdt instruction had been executed. only execu- tion of this instruction without the other preclear instruction, sets the indicating flag which implies this instruction was executed. the pd and to flags remain unchanged. operation wdt and wdt prescaler ? 00h* pd and to ? 0* affected flag(s) tc2 tc1 to pd ov z ac c C C0*0*CCCC cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1s comple- ment). bits which previously contain a one are changed to zero and vice- versa. operation [m] ? [ m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC HT48CA0 24 23rd july 98
cpla [m] complement data memory and place result in accumulator description each bit of the specified data memory is logically complemented (1s comple- ment). bits which previously contained a one are changed to zero and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc ? [ m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary code decimal) code. the accumulator is divided into two nibbles. each nibble is adjusted to bcd code and an internal carry (ac1) will be created if the low nibble of the accumulator is greater than 9. the bcd adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if (acc.3~acc.0) >9 or ac=1 then ([m].3~[m].0) ? (acc.3~acc.0)+6, ac1= ac else ([m].3~[m].0) ? (acc.3~acc.0), ac1=0 if (acc.7~acc.4)+ac1 >9 or c=1 then ([m].7~[m].4) ? (acc.7~acc.4)+6+ac1, c=1 else ([m].7~[m].4) ? (acc.7~acc.4)+ac1, c=c affected flag(s) tc2 tc1 to pd ov z ac c CCCCC C ? dec [m] decrement data memory description data in the specified data memory is decremented by one operation [m] ? [m]C1 affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC HT48CA0 25 23rd july 98
deca [m] decrement data memory and place result in accumulator description data in the specified data memory is decremented by one, leaving the result in the accumulator. the contents of the data memory remain unchanged. operation acc ? [m]C1 affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pd) is set and the wdt time-out bit (to) is cleared. operation pc ? pc+1 pd ? 1 to ? 0 affected flag(s) tc2 tc1 to pd ov z ac c C C 01CCCC inc [m] increment data memory description data in the specified data memory is incremented by one. operation [m] ? [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC inca [m] increment data memory and place result in accumulator description data in the specified data memory is incremented by one, leaving the result in the accumulator. the contents of the data memory remain unchanged. operation acc ? [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC HT48CA0 26 23rd july 98
jmp addr direct jump description bits 0~9 of the program counter are replaced with the directlyCspecified address unconditionally, and control passed to this destination. operation pc ? addr affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC mov a,[m] move data memory to accumulator description the contents of the specified data memory is copied to the accumulator. operation acc ? [m] affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC mov a,x move immediate data to accumulator description the 8Cbit data specified by the code is loaded into the accumulator. operation acc ? x affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC mov [m],a move accumulator to data memory description the contents of the accumulator is copied to the specified data memory (one of the data memory locations). operation [m] ? acc affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC nop no operation description no operation is performed. execution continues with the next instruction. operation pc ? pc+1 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC or a,[m] logical or accumulator with data memory HT48CA0 27 23rd july 98
description data in the accumulator and the specified data memory (one of the data memory locations) performs a bitwise logical_or operation. the result is stored in the accumulator. operation acc ? acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC or a,x logical or immediate data to accumulator description data in the accumulator and the specified data performs a bitwise logical_or operation. the result is stored in the accumulator. operation acc ? acc or x affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC orm a,[m] logical or data memory with accumulator description data in the data memory (one of the data memory locations) and the accumulator performs a bitwise logical_or operation. the result is stored in the data memory. operation [m] ? acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC ret return from subroutine description the program counter is restored from the stack. this is a two-cycle instruc- tion. operation pc ? stack affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC HT48CA0 28 23rd july 98
ret a,x return and place immediate data in accumulator description the program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. operation pc ? stack acc ? x affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC reti return from interrupt description the program counter is restored from the stack, and interrupts enabled by setting the emi bit. emi is the enable master (global) interrupt bit (bit 0; register intc). operation pc ? stack emi ? 1 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC rl [m] rotate data memory left description the contents of the specified data memory is rotated left one bit with bit 7 rotated into bit 0. operation [m].(i+1) ? [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ? [m].7 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC rla [m] rotate data memory left and place result in accumulator description data in the specified data memory is rotated left one bit with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) ? [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 ? [m].7 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC HT48CA0 29 23rd july 98
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are together rotated left one bit. bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) ? [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ? c c ? [m].7 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCC ? rlca [m] rotate left through carry and place result in accumulator description data in the specified data memory and the carry flag are together rotated left one bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) ? [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 ? c c ? [m].7 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCC ? rr [m] rotate data memory right description the contents of the specified data memory are rotated right one bit with bit 0 rotated to bit 7. operation [m].i ? [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ? [m].0 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC rra [m] rotate right and place result in accumulator description data in the specified data memory is rotated one bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) ? [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 ? [m].0 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC HT48CA0 30 23rd july 98
rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated one bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i ? [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ? c c ? [m].0 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCC ? rrca [m] rotate right through carry and place result in accumulator description data of the specified data memory and the carry flag are together rotated one bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i ? [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 ? c c ? [m].0 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCC ? sbc a,[m] subtract data memory and carry from accumulator description the contents of the specified data memory and the complement of the carry flag are together subtracted from the accumulator, leaving the result in the accumulator. operation acc ? acc+[ m]+c affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? sbcm a,[m] subtract data memory and carry from accumulator description the contents of the specified data memory and the complement of the carry flag are together subtracted from the accumulator, leaving the result in the data memory. operation [m] ? acc+[ m]+c affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? HT48CA0 31 23rd july 98
sdz [m] skip if decrement data memory is zero description the contents of the specified data memory are decremented by one. if the result is zero, the next instruction is skipped. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this makes a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if ([m]C1)=0, [m] ? ([m]C1) affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC sdza [m] decrement data memory and place result in acc, skip if zero description the contents of the specified data memory are decremented by one. if the result is zero, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction, that makes a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if ([m]C1)=0, acc ? ([m]C1) affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC set [m] set data memory description each bit of the specified data memory is set to one. operation [m] ? ffh affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC set [m].i set bit of data memory description bit i of the specified data memory is set to one. operation [m].i ? 1 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC HT48CA0 32 23rd july 98
siz [m] skip if increment data memory is zero description the contents of the specified data memory is incremented by one. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if ([m]+1)=0, [m] ? ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC siza [m] increment data memory and place result in acc, skip if zero description the contents of the specified data memory is incremented by one. if the result is zero, the next instruction is skipped and the result is stored in the accumulator. the data memory remains unchanged. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if ([m]+1)=0, acc ? ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC snz [m].i skip if bit i of the data memory is not zero description if bit i of the specified data memory is not zero, the next instruction is skipped. if bit i of the data memory is not zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if [m].i 1 0 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC sub a,[m] subtract data memory from accumulator description the specified data memory is subtracted from the contents of the accumula- tor, leaving the result in the accumulator. operation acc ? acc+[ m]+1 affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? HT48CA0 33 23rd july 98
subm a,[m] subtract data memory from accumulator description the specified data memory is subtracted from the contents of the accumula- tor, leaving the result in the data memory. operation [m] ? acc [ m]+1 affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? sub a,x subtract immediate data from accumulator description the immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc ? acc+ x+1 affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (one of the data memory locations) are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC swapa [m] swap data memory and place result in accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 ? [m].7~[m].4 acc.7~acc.4 ? [m].3~[m].0 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC HT48CA0 34 23rd july 98
sz [m] skip if data memory is zero description if the contents of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a 2- cycle instruction. otherwise proceed with the next instruction. operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC sza [m] move data memory to acc, skip if zero description the contents of the specified data memory is copied to the accumulator. if the contents is zero, the following instruction, fetched during the current instruc- tion execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC sz [m].i skip if bit i of the data memory is zero description if bit i of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if [m].i=0 affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC tabrdc [m] move rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] ? rom code (low byte) tblh ? rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC HT48CA0 35 23rd july 98
tabrdl [m] move rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] ? rom code (low byte) tblh ? rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c C C CCCCCC xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory performs a bitwise logical exclusive_or operation and the result is stored in the accumulator. operation acc ? acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC xorm a,[m] logical xor data memory with accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclusive_or operation. the result is stored in the data memory. the zero flag is affected. operation [m] ? acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC xor a,x logical xor immediate data to accumulator description data in the the accumulator and the specified data perform a bitwise logical exclusive_or operation. the result is stored in the accumulator. the zero flag is affected. operation acc ? acc xor x affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC HT48CA0 36 23rd july 98

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